Protecting high-voltage devices from ESD events poses difficult challenges, challenges that are not adequately solved by devices in the prior art. As one example, self-protected double diffused metal-oxide semiconductor (“DMOS”) devices have low holding voltages and are latch-up sensitive. Because these devices cannot remove themselves from a high-current mode, they are easily destroyed. Furthermore, these devices show unstable performance. Because a DMOS device is not designed to uniformly carry current, a portion of the device may be destroyed before the rest can turn ON and shunt ESD current to ground.
Other prior art devices rely on stacking low-voltage snapback structures. One drawback of these devices is that they may have a turn ON voltage above the breakdown voltage of the device being protected. Another drawback is that they cannot be finely tuned. Their operating voltage is increased by “stacking” individual low-voltage snapback elements. Accordingly, the voltage can only be increased by discrete amounts and cannot be precisely scaled to specific applications.
Still other prior art structures use an active-drive core clamp. These clamps use an RC circuit to control the DMOS gate to make it turn ON during an ESD event and then OFF after the ESD event dissipates. Such circuits may be adequate for low-voltage devices, but because the RC component must also operate at high voltages, these components may not be available for high-voltage and may require a relatively large layout area.